1. Field of the Invention
The present invention is related to a method and apparatus for enhancing data rate of an advanced micro-controller bus architecture, and more particularly, to a method and apparatus, used in the advanced micro-controller bus architecture, for controlling peripheral slave devices via directly receiving control signals outputted from more than one master device.
2. Description of the Prior Art
With rapid development of integrated circuit technology, the integration level of a chip has been developed higher and higher, and thereby integrating a complex system into an independent System-on-Chip (SoC) becomes achievable. Compared to a system formed on a circuit board, the SoC has advantages of weight, volume, performance, cost and so on. However, since the SoC implements a complete system, signal transmissions in the SoC become complicated. Therefore, the prior art provides an advanced micro-controller bus architecture (AMBA) for accomplishing an on-chip bus.
The AMBA, provided by ARM Corporation for a high-performance embedded system bus, is an open and free protocol, which defines Advanced High-Performance Bus (AHB), Advanced System Bus (ASB), Advanced Peripheral Bus (APB), Test Methodology, and so on. The AHB and ASB are applicable to high-performance and high clock-rate system modules, where the ASB adopts a bidirectional data bus to read and write data. The APB is applicable to low power-consumption external devices, detailed description of which can be downloaded from an ARM website “www.arm.com”. Brief description of Advanced High-Performance Bus and Advanced Peripheral Bus is described as follows.
Please refer to FIG. 1. FIG. 1 depicts a schematic diagram of a prior art AMBA SoC 10. The SoC 10 comprises an AHB system 12, an APB system 14, and a bridge 16 between the AHB system 12 and the APB system 14. The AHB system 12 comprises master devices (such as embedded processors, direct memory access controllers or other auxiliary operators), slave devices (such as memory or other devices demanding wide bandwidths), and an infrastructure. Within the AHB system 12, all signal transmissions are delivered by the master devices and responded by the slave devices. The infrastructure of the AHB system 12 comprises an arbitrator, a master-to-slave multiplexer, a slave-to-master multiplexer, a decoder, dummy slaves, and dummy masters. What makes the AHB system 12 demand the arbitrator is that the AHB system 12 is a multi-master and pipeline-operation system, allowing only one master device using bus resources at one time. The Decoder takes a task on address decoding, so as to choose one of the slave devices to respond transmission. The multiplexers manager bus-routing for avoiding utilizing a tri-state bus.
The APB system 14 mainly implements a low-speed and low-power-consumption external bus for connecting peripheral devices demanding lower bandwidth, such as an Universal Asynchronous Receiver/Transmitter (UART), IEEE 1284 interface, timers . . . etc. Unlike the architecture of the AHB system 12, which is a multi-master structure, the APB system 14 has only one master device, the bridge 16. Therefore, the APB system 14 is much more uncomplicated than the AHB system 12, so that the APB system 14 does not need arbitrators and request or grant signals, and is not a pipeline system.
As mentioned above, the AHB system 12 is a multi-master and pipeline-operation system, allowing only one master using bus resources at one time, and thereby the APB system 14 is under control of the AHB system 12 via the bridge 16. Therefore, the bridge 16 can be seen as a slave device with regard to the AHB system 12, and seen as the only one master device with regard to the APB system 14. In other words, since there is only one master device allowed using bus resources at one time in the AHB system 12 and the APB system 14 is under control of the master, efficiency and bandwidth-utility rate of the APB system 14 are restricted by procedures of the AHB system 12. That is, even if there are available system resources, the system resources may be wasted because the APB system 14 must be under control of the AHB system 12. Thus, efficiency and bandwidth-utility rate of the APB system 14 cannot be increased.
Therefore, the prior art AMBA is unable to enhance the efficiency of the APB, which influences on allocation and use of system resources and thereby decreases data-processing speed of the SoC 10.